Broadcom BCM5722 - Page 20

BCM5722 Programmer’s Guide
10/15/07
BM Hardware Diagnostic 3 Register (Offset 0x4454)..........................................................................310
Receive Flow Threshold Register (Offset 0x4458)..............................................................................310
Read DMA Control Registers...................................................................................................................311
Read DMA Mode Register (Offset 0x4800).........................................................................................311
Read DMA Status Register (Offset 0x4804)........................................................................................313
Read DMA Programmable IPv6 Extension Header Register (Offset: 0x4808) ...................................313
Write DMA Control Registers ..................................................................................................................314
Write DMA Mode Register (Offset 0x4C00) ........................................................................................314
Write DMA Status Register (Offset 0x4C04) .......................................................................................315
RX RISC Registers....................................................................................................................................317
RX RISC Mode Register (Offset 0x5000)............................................................................................317
RX RISC State Register (Offset 0x5004) ............................................................................................318
RX RISC Program Counter (Offset 0x501C).......................................................................................320
RX RISC Hardware Breakpoint Register (Offset 0x5034)...................................................................320
Virtual CPU Registers (BCM5906 Only)..................................................................................................321
VCPU Status Register (Offset 0x5100) ...............................................................................................321
Device Configuration Shadow Register (Offset 0x5104).....................................................................322
Virtual CPU Holding Register (Offset 0x5108) ....................................................................................322
Virtual CPU Data Register (Offset 0x510c) .........................................................................................322
Virtual CPU Debug Register (Offset 0x5110)......................................................................................323
Virtual CPU Shadow 1 Register (Offset 0x5114).................................................................................323
Virtual CPU Shadow 2 Register (Offset 0x5118).................................................................................323
Low-Priority Mailboxes ............................................................................................................................324
Interrupt Mailbox 0 Register (Offset 0x5800–0x5807).........................................................................325
Receive BD Standard Producer Ring Index Register (Offset 0x5868–0x586F)..................................325
Receive BD Return Ring 1 Consumer Index Register (Offset 0x5880–0x5887).................................325
Receive BD Return Ring 2 Consumer Index Register (Offset 0x5888–0x588F).................................325
Receive BD Return Ring 3 Consumer Index Register (Offset 0x5890–0x5897).................................325
Receive BD Return Ring 2 Consumer Index Register (Offset 0x5898–0x589F).................................325
Send BD Ring Host Producer Indices Registers (Offset 0x5900–0x5907)..........................................325
ISO Send BD Ring Host Producer Indices Registers (Offset 0x5908–0x590F) ..................................325
Flow-Through Queues..............................................................................................................................326
FTQ Reset Register (Offset 0x5C00) ..................................................................................................326
MAC TX FIFO Enqueue Register (Offset 0x5CB8) .............................................................................327