Broadcom BCM5722 - Page 55

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Page lv
0x7C5C).......................................................................................................................................... 393
Table 435: Split Controller Misc 0 Register Diagnostic Register (Offset 0x7C60).......................................... 394
Table 436: Split Controller Misc 1 Register Diagnostic Register (Offset 0x7C64).......................................... 394
Table 437: TLP Status Register (Offset 0x7C60)........................................................................................... 394
Table 438: TLP Status Register (Offset 0x7C60)........................................................................................... 395
Table 439: Data Link Control Register (Offset 0x7D00)................................................................................. 395
Table 440: Data Link Status Register (Offset 0x7D04) .................................................................................. 397
Table 441: Data Link Attention Register (Offset 0x7D08) .............................................................................. 398
Table 442: Data Link Attention Mask Register (Offset 0x7D0C) ....................................................................398
Table 443: Next Transmit Sequence Number Debug Register (Offset 0x7D10)............................................ 399
Table 444: ACKed Transmit Sequence Number Debug Register (Offset 0x7D14)........................................ 399
Table 445: Purged Transmit Sequence Number Debug Register (Offset 0x7D18)........................................ 399
Table 446: Receive Sequence Number Debug Register (Offset 0x7D1C)..................................................... 399
Table 447: Data Link Replay Register (Offset 0x7D20) ................................................................................. 399
Table 448: Data Link ACK Timeout Register (Offset 0x7D24) .......................................................................400
Table 449: Power Management Threshold Register (Offset 0x7D28)............................................................ 400
Table 450: Retry Buffer Write Pointer Debug Register (Offset 0x7D2C)........................................................ 400
Table 451: Retry Buffer Read Pointer Debug Register (Offset 0x7D30)........................................................ 400
Table 452: Retry Buffer Purged Pointer Debug Register (Offset 0x7D34)..................................................... 401
Table 453: Retry Buffer Read/Write Debug Port (Offset 0x7D38).................................................................. 401
Table 454: Error Count Threshold Register (Offset 0x7D3C)......................................................................... 401
Table 455: TLP Error Counter Register (Offset 0x7D40) ............................................................................... 401
Table 456: DLLP Error Counter (Offset 0x7D44) ........................................................................................... 402
Table 457: NAK Received Counter (Offset 0x7D48)...................................................................................... 402
Table 458: Data Link Test Register (Offset 0x7D4C)..................................................................................... 402
Table 459: Packet BIST Register (Offset 0x7D50)......................................................................................... 403
Table 460: Link PCIe 1.1 Control Register (0x7D54) ..................................................................................... 404
Table 461: PHY Mode Register (Offset 0x7E00)............................................................................................ 405
Table 462: PHY/Link Status Register (Offset 0x7E04)................................................................................... 405
Table 463: PHY/Link LTSSM Control Register (Offset 0x7E08) .................................................................... 406
Table 464: PHY/Link Training Link Number (Offset 0x7E0C) ........................................................................406
Table 465: PHY/Link Training Lane Number (Offset 0x7E10)........................................................................406
Table 466: PHY/Link Training N_FTS (Offset 0x7E14).................................................................................. 407
Table 467: PHY Attention Register (Offset 0x7E18) ...................................................................................... 407
Table 468: PHY Attention Mask Register (Offset 0x7E1C) ............................................................................ 408