Chapter 6
180 MIPS R4000 Microprocessor User's Manual
Prep and Cleanup Cycle Overlap. Τhe adder does not allow the
preparation (U stage) and cleanup cycles (N, A, R) of a division instruction
to be pipelined with any other instruction; however, the adder does allow
the last cycle of preparation or cleanup to be overlapped one clock by the
following instruction’s U stage (the CPU EX cycle). Figure 6-18 shows this
process.
Figure 6-18 Adder Prep and Cleanup Cycle Overlap
A+D R+D
. . .
DIV.D
or
U A R+D D D D A+D R+D A R
DIV.D
U A S+R S+D D
. . .
D A+D R+D A+D R+D A R
NOP U
NOP
U
. . .
NOP
U S+A A+R R+SADD.[S,D]
U
. . .
. . .
. . .
NOP
U
UAR
CMP.[S,D]
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