Mips Technologies R4000 - Page 209

MIPS R4000 Microprocessor User's Manual 179
Floating-Point Unit
†
While there is no resource conflict in issuing this CMP.[S,D] instruction, the hardware does
not allow it.
Figure 6-16 MUL.D and CMP.[S,D] Cleanup Cycle Conflict in FPU Adder
†
While there is no resource conflict in issuing this CMP.[S,D] instruction, the hardware does
not allow it.
Figure 6-17 MUL.S and CMP.[S,D] Cleanup Cycle Conflict in FPU Adder
– – – – – – – – – – – – – – – – –
– – – – – – – – – – – – – –
– – – – – – – – – – –
– – – – – – – – –
– – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – – – – – – – – –
UMMMMN N/A R
MUL.D
UAR
CMP.[S,D]
Yes
Yes
No
†
No
Yes
Yes
Yes
1234567 8910
Stage#
UAR
UAR
UAR
UAR
UAR
UAR
Indicates a resource conflict
I1
I2
I3
I4
I5
I6
I7
I8
Legal to Issue?
– – – – – – – – – – – – – – – – –
– – – – – – – – – – – – – –
– – – – – – – – – – –
– – – – – – – – –
– – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – – – – – – – – –
UMMMN N/A R
MUL.S
UAR
CMP.[S,D]
Yes
No
†
No
Yes
Yes
Yes
Yes
1234 567 8910
Stage#
UAR
UAR
UAR
UAR
UAR
UAR
Indicates a resource conflict
I1
I2
I3
I4
I5
I6
I7
I8
Legal to Issue?