Mips Technologies R4000 - Page 208

Chapter 6
178 MIPS R4000 Microprocessor User's Manual
Resource Conflict. The adder must allow the cleanup stages (A, R) of a
multiplication instruction to be pipelined with the execution of an
ADD.[S,D], SUB.[S,D], or C.COND.[S,D] instruction, as long as no two
instructions simultaneously attempt to use the same A and R pipe stages.
For instance, Figure 6-14 shows a resource conflict between the mantissa
add (A, stage 7) of instructions 1, 5, and 6. This figure also shows the
resource conflict between result round (R), stage 8, of instructions 1, 5, and
6. The multiplication cleanup cycles (A, R) can neither overlap nor
pipeline with any other instruction currently in the adder pipe.
Figures 6-14 through 6-17 show these constraints.
Figure 6-14 MUL.D and ADD.[S,D] Cycle Conflict in FPU Adder
Figure 6-15 MUL.S and ADD.[S,D] Cycle Conflict in FPU Adder
– – – – – – – – – – – – – – – – –
– – – – – – – – – – – – – –
– – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – – – – – – – – –
UMMMMN
MUL.D
U S+A A+R R+S
ADD.[S,D]
U S+A A+R R+S
U S+A A+R R+S
U S+A
U R+S
U S+A A+R R+S
U S+A A+R R+S
Yes
Yes
No
No
Yes
Yes
Yes
1 2 3 4 5 6 7 8 9 10 11
Stage#
I1
I2
I3
I4
I5
I6
I7
I8
S+A A+R
A+R R+S
N/A R
Indicates a resource conflict
Legal to Issue?
– – – – – – – – – – –
– – – – – – – – –
– – – – – – – – – – – – – – – – – – – – – – – – – –
UMMMN
MUL.S
U S+A A+R R+S
ADD.[S,D]
U S+A A+R R+S
U S+A R+S
U
R+S
U S+A A+R R+S
U S+A A+R R+S
U S+A A+R R+S
Yes
No
No
Yes
Yes
Yes
Yes
1 2 3 4 5 6 7 8 9 10 11
Stage#
S+A
A+R
N/A R
A+R
Indicates a resource conflict
I1
I2
I3
I4
I5
I6
I7
I8
Legal to Issue?
– – – – – – – – – – – – – – – – –
– – – – – – – – – – – – – –
– – – – – – – – – – –
– – – – – – – – –
– – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – – – – – – – – –