MIPS R4000 Microprocessor User's Manual 339
System Interface
Figure 12-24 Two Processor Write Requests, Second Write Delayed for the Assertion of WrRdy*
Figure 12-25 Processor Read Request within a Cluster Delayed for the Assertion of RdRdy*
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Addr Data0 Addr Data0
SysCmd Bus
Write NEOD Write NEOD
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
4
2
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Addr Addr Data0 Addr Data0 Data1 Data2 Data3
SysCmd Bus
Read Upd CEOD Write CData CData CData CEOD
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
1
3
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