Chapter 12
340 MIPS R4000 Microprocessor User's Manual
Figure 12-26 Processor Write Request within a Cluster Delayed for the Assertion of WrRdy*
Figure 12-27 Processor Write Request Delayed for the Assertion of WrRdy* and the Completion
of an External Invalidate Request
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Addr Addr Data0 Addr Data0 Data1 Data2 Data3
SysCmd Bus
Read Upd CEOD Write CData CData CData CEOD
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
2
4
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Addr Addr Unsd Addr Data0
SysCmd Bus
Write Ivd CEOD Write NEOD
ValidOut*
ValidIn*
RdRdy*
WrRdy*
ExtRqst*
Release*
2
4
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