MIPS R4000 Microprocessor User's Manual A-9
CPU Instruction Set Details
A.5 Jump and Branch Instructions
All jump and branch instructions have an architectural delay of exactly
one instruction. That is, the instruction immediately following a jump or
branch (that is, occupying the delay slot) is always executed while the
target instruction is being fetched from storage. A delay slot may not itself
be occupied by a jump or branch instruction; however, this error is not
detected and the results of such an operation are undefined.
If an exception or interrupt prevents the completion of a legal instruction
during a delay slot, the hardware sets the EPC register to point at the jump
or branch instruction that precedes it. When the code is restarted, both the
jump or branch instructions and the instruction in the delay slot are
reexecuted.
Because jump and branch instructions may be restarted after exceptions or
interrupts, they must be restartable. Therefore, when a jump or branch
instruction stores a return link value, register 31 (the register in which the
link is stored) may not be used as a source register.
Since instructions must be word-aligned, a Jump Register or Jump and
Link Register instruction must use a register whose two low-order bits are
zero. If these low-order bits are not zero, an address exception will occur
when the jump target instruction is subsequently fetched.
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