Appendix A
A-10 MIPS R4000 Microprocessor User's Manual
A.6 Coprocessor Instructions
Coprocessors are alternate execution units, which have register files
separate from the CPU. The MIPS architecture provides four coprocessor
units, or classes, and these coprocessors have two register spaces, each
space containing thirty-two 32-bit registers.
• The first space, coprocessor general registers, may be directly
loaded from memory and stored into memory, and their
contents may be transferred between the coprocessor and
processor.
• The second space, coprocessor control registers, may only have
their contents transferred directly between the coprocessor and
the processor. Coprocessor instructions may alter registers in
either space.
A.7 System Control Coprocessor (CP0) Instructions
There are some special limitations imposed on operations involving CP0
that is incorporated within the CPU. Although load and store instructions
to transfer data to/from coprocessors and to move control to/from
coprocessor instructions are generally permitted by the MIPS architecture,
CP0 is given a somewhat protected status since it has responsibility for
exception handling and memory management. Therefore, the move to/
from coprocessor instructions are the only valid mechanism for writing to
and reading from the CP0 registers.
Several CP0 instructions are defined to directly read, write, and probe TLB
entries and to modify the operating modes in preparation for returning to
User mode or interrupt-enabled states.
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