Mips Technologies R4000 - Page 485

MIPS R4000 Microprocessor User's Manual A-17
CPU Instruction Set Details
Format:
BCzF offset
Description:
A branch target address is computed from the sum of the address of the
instruction in the delay slot and the 16-bit offset, shifted left two bits and
sign-extended. If coprocessor z’s condition signal (CpCond), as sampled
during the previous instruction, is false, then the program branches to the
target address with a delay of one instruction.
Because the condition line is sampled during the previous instruction,
there must be at least one instruction between this instruction and a
coprocessor instruction that changes the condition line.
Operation:
*See the table “Opcode Bit Encoding” on next page, or “CPU Instruction
Opcode Bit Encoding” at the end of Appendix A.
BCzF
Branch On Coprocessor z False
5
16 15
BC
31 2526
COPz
6
0
16
offsetBCF
21 20
5
0 1 0 0 x x* 0 1 0 0 0 0 0 0 0 0
BCzF
T: target ← (offset
15
)
14
|| offset || 0
2
32 T–1: condition ← not COC[z]
T+1: if condition then
PC ← PC + target
endif
T: target ← (offset
15
)
46
|| offset || 0
2
64 T–1: condition ← not COC[z]
T+1: if condition then
PC ← PC + target
endif