MIPS R4000 Microprocessor User's Manual A-29
CPU Instruction Set Details
Format:
BGEZALL rs, offset
Description:
A branch target address is computed from the sum of the address of the
instruction in the delay slot and the 16-bit offset, shifted left two bits and
sign-extended. Unconditionally, the address of the instruction after the
delay slot is placed in the link register, r31. If the contents of general
register rs have the sign bit cleared, then the program branches to the
target address, with a delay of one instruction. General register rs may not
be general register 31, because such an instruction is not restartable. An
attempt to execute this instruction is not trapped, however. If the
conditional branch is not taken, the instruction in the branch delay slot is
nullified.
Operation:
Exceptions:
None
BGEZALL
Or Equal To Zero
Branch On Greater Than
31 2526 2021 1516 0
REGIMM rs BGEZALL
offset
655 16
0 0 0 0 0 1 1 0 0 1 1
BGEZALL
And Link Likely
32 T: target ← (offset
15
)
14
|| offset || 0
2
condition ← (GPR[rs]
31
= 0)
T+1: if condition then
PC ← PC + target
endif
GPR[31] ← PC + 8
NullifyCurrentInstruction
else
64 T: target ← (offset
15
)
46
|| offset || 0
2
condition ← (GPR[rs]
63
= 0)
T+1: if condition then
PC ← PC + target
endif
GPR[31] ← PC + 8
NullifyCurrentInstruction
else
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