Appendix A
A-40 MIPS R4000 Microprocessor User's Manual
Format:
BNEL rs, rt, offset
Description:
A branch target address is computed from the sum of the address of the
instruction in the delay slot and the 16-bit offset, shifted left two bits and
sign-extended. The contents of general register rs and the contents of
general register rt are compared. If the two registers are not equal, then
the program branches to the target address, with a delay of one
instruction.
If the conditional branch is not taken, the instruction in the branch delay
slot is nullified.
Operation:
Exceptions:
None
BNEL
Branch On Not Equal Likely
31 2526 2021 1516 0
BNEL rs rt
offset
655 16
0 1 0 1 0 1
BNEL
32 T: target ← (offset
15
)
14
|| offset || 0
2
condition ← (GPR[rs] ≠ GPR[rt])
T+1: if condition then
PC ← PC + target
else
endif
NullifyCurrentInstruction
64 T: target ← (offset
15
)
46
|| offset || 0
2
condition ← (GPR[rs] ≠ GPR[rt])
T+1: if condition then
PC ← PC + target
else
endif
NullifyCurrentInstruction
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