Appendix A
A-42 MIPS R4000 Microprocessor User's Manual
Format:
CACHE op, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. The virtual address is translated to
a physical address using the TLB, and the 5-bit sub-opcode specifies a
cache operation for that address.
If CP0 is not usable (User or Supervisor mode) the CP0 enable bit in the
Status register is clear, and a coprocessor unusable exception is taken. The
operation of this instruction on any operation/cache combination not
listed below, or on a secondary cache when none is present, is undefined.
The operation of this instruction on uncached addresses is also undefined.
The Index operation uses part of the virtual address to specify a cache
block.
For a primary cache of 2
CACHEBITS
bytes with 2
LINEBITS
bytes per tag,
vAddr
CACHEBITS ... LINEBITS
specifies the block.
For a secondary cache of 2
CACHEBITS
bytes with 2
LINEBITS
bytes per tag,
pAddr
CACHEBITS ... LINEBITS
specifies the block.
Index Load Tag also uses vAddr
LINEBITS... 3
to select the doubleword for
reading ECC or parity. When the CE bit of the Status register is set, Hit
WriteBack, Hit WriteBack Invalidate, Index WriteBack Invalidate, and Fill
also use vAddr
LINEBITS ... 3
to select the doubleword that has its ECC or
parity modified. This operation is performed unconditionally.
The Hit operation accesses the specified cache as normal data references,
and performs the specified operation if the cache block contains valid data
with the specified physical address (a hit). If the cache block is invalid or
contains a different address (a miss), no operation is performed.
CACHE
Cache
31 2526 2021 1516 0
CACHE base op
offset
655 16
1 0 1 1 1 1
CACHE
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