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Mips Technologies R4000 - Page 520

Mips Technologies R4000
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Appendix A
A-52 MIPS R4000 Microprocessor User's Manual
Format:
DADDI rt, rs, immediate
Description:
The 16-bit immediate is sign-extended and added to the contents of general
register rs to form the result. The result is placed into general register rt.
An overflow exception occurs if carries out of bits 62 and 63 differ (2’s
complement overflow). The destination register rt is not modified when
an integer overflow exception occurs.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
Exceptions:
Integer overflow exception
Reserved instruction exception (R4000 in 32-bit mode)
DADDI
Doubleword Add Immediate
31 2526 2021 1516 0
DADDI
rs rt
immediate
655 16
0 1 1 0 0 0
DADDI
64 T: GPR [rt] GPR[rs] + (immediate
15
)
48
|| immediate
15...0

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