Mips Technologies R4000 - Page 528

Appendix A
A-60 MIPS R4000 Microprocessor User's Manual
Operation:
Exceptions:
None
(continued)
DIVU
Divide Unsigned
DIVU
← undefined
← undefined
← undefined
HI ← (0 || GPR[rs]) mod (0 || GPR[rt])
T–2: LO ← undefined
T: LO ← (0 || GPR[rs]) div (0 || GPR[rt])
HI
T–1: LO
HI
← undefined
← undefined
← undefined
T–2: LO ← undefined
T: q ← (0 || GPR[rs]
31...0
) div (0 || GPR[rt]
31...0
)
HI
T–1: LO
HI
LO ← (q
31
)
32
|| q
31...0
HI ← (r
31
)
32
|| r
31...0
r ← (0 || GPR[rs]
31...0
) mod (0 || GPR[rt]
31...0
)
32
64