MIPS R4000 Microprocessor User's Manual A-73
CPU Instruction Set Details
Format:
DSRL32 rd, rt, sa
Description:
The contents of general register rt are shifted right by 32+sa bits, inserting
zeros into the high-order bits. The result is placed in register rd.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
Exceptions:
Reserved instruction exception (R4000 in 32-bit mode)
DSRL32
Doubleword Shift Right
31 2526 2021 1516
SPECIAL rt
655
rd sa DSRL32
55 6
11 10 6 5 0
0 0 0 0 0 0 1 1 1 1 1 0
DSRL32
Logical + 32
0
0 0 0 0 0
64 T: s ← 1 || sa
GPR[rd] ← 0
s
|| GPR[rt]
63...s
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