Appendix A
A-74 MIPS R4000 Microprocessor User's Manual
Format:
DSUB rd, rs, rt
Description:
The contents of general register rt are subtracted from the contents of
general register rs to form a result. The result is placed into general
register rd.
The only difference between this instruction and the DSUBU instruction is
that DSUBU never traps on overflow.
An integer overflow exception takes place if the carries out of bits 62 and
63 differ (2’s complement overflow). The destination register rd is not
modified when an integer overflow exception occurs.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
Exceptions:
Integer overflow exception
Reserved instruction exception (R4000 in 32-bit mode)
DSUB
DSUB
Doubleword Subtract
31 2526 2021 1516
SPECIAL rs rt
655
rd 0 DSUB
55 6
11 10 6 5 0
0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0
64 T: GPR[rd] ← GPR[rs] – GPR[rt]
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