MIPS R4000 Microprocessor User's Manual A-75
CPU Instruction Set Details
Format:
DSUBU rd, rs, rt
Description:
The contents of general register rt are subtracted from the contents of
general register rs to form a result. The result is placed into general
register rd.
The only difference between this instruction and the DSUB instruction is
that DSUBU never traps on overflow. No integer overflow exception
occurs under any circumstances.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
Exceptions:
Reserved instruction exception (R4000 in 32-bit mode)
DSUBU
Doubleword Subtract Unsigned
31 2526 2021 1516
SPECIAL rs rt
655
rd 0 DSUBU
55 6
11 10 6 5 0
0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1
DSUBU
64 T: GPR[rd] ā GPR[rs] ā GPR[rt]
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