Mips Technologies R4000 - Page 550

Appendix A
A-82 MIPS R4000 Microprocessor User's Manual
Format:
LBU rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. The contents of the byte at the
memory location specified by the effective address are zero-extended and
loaded into general register rt.
Operation:
Exceptions:
TLB refill exception TLB invalid exception
Bus error exception Address error exception
LBU
Load Byte Unsigned
31 2526 2021 1516 0
LBU base rt
offset
655 16
1 0 0 1 0 0
LBU
T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE – 1 ...3
|| (pAddr
2...0
xor ReverseEndian
3
)
mem ← LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)
byte ← vAddr
2...0
xor BigEndianCPU
3
GPR[rt] ← 0
24
|| mem
7+8* byte...8* byte
T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE – 1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
mem ← LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)
byte ← vAddr
2...0
xor BigEndianCPU
3
GPR[rt] ← 0
56
|| mem
7+8* byte...8* byte
32
64