MIPS R4000 Microprocessor User's Manual A-83
CPU Instruction Set Details
Format:
LD rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. The contents of the 64-bit
doubleword at the memory location specified by the effective address are
loaded into general register rt.
If any of the three least-significant bits of the effective address are non-
zero, an address error exception occurs.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
Reserved instruction exception (R4000 in 32-bit user mode
R4000 in 32-bit supervisor mode)
LD
Load Doubleword
31 2526 2021 1516 0
LD base rt
offset
655 16
1 1 0 1 1 1
LD
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
mem ← LoadMemory (uncached, DOUBLEWORD, pAddr, vAddr, DATA)
GPR[rt] ← mem
To Next Page
Loading...