Mips Technologies R4000 - Page 559

MIPS R4000 Microprocessor User's Manual A-91
CPU Instruction Set Details
Given a doubleword in a register and a doubleword in memory, the
operation of LDR is as follows:
LEM Little-endian memory (BigEndianMem = 0)
BEM BigEndianMem = 1
Type AccessType (see Table 2-1) sent to memory
Offset pAddr
2...0
sent to memory
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
Reserved instruction exception (R4000 in 32-bit mode)
(continued)
LDR
Load Doubleword Right
LDR
LDR
ACDB
Register
IKLJ
Memory
EGHF
MOPN
0 I J KLMNOP 7 0 0 ABCDEFGI 0 7 0
1 A I J KL MNO 6 1 0 ABCDEFI J 1 6 0
2 A BI JKLMN 5 2 0 AB CDEI J K 2 5 0
3 A BCI J KLM 4 3 0 ABCDI JK L 3 4 0
4ABCDIJKL340ABCIJKLM430
5ABCDEIJK250ABIJKLMN520
6ABCDEFIJ160AIJKLMNO610
7ABCDEFGI070IJKLMNOP700
BigEndianCPU = 0
vAddr
2..0
destination
destination
type
type
offset
offset
BigEndianCPU = 1
LEM BEM
LEM BEM