Appendix A
A-90 MIPS R4000 Microprocessor User's Manual
The contents of general register rt are internally bypassed within the
processor so that no NOP is needed between an immediately preceding
load instruction which specifies register rt and a following LDR (or LDL)
instruction which also specifies register rt.
No address exceptions due to alignment are possible.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
(continued)
LDR
Load Doubleword Right
LDR
endif
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE–1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
pAddr ← pAddr
31...3
|| 0
3
GPR[rt] ← GPR[rt]
63...64-8*byte
|| mem
63...8*byte
mem ← LoadMemory (uncached, byte, pAddr, vAddr, DATA)
if BigEndianMem = 1 then
byte ← vAddr
2...0
xor BigEndianCPU
3
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