Mips Technologies R4000 - Page 557

MIPS R4000 Microprocessor User's Manual A-89
CPU Instruction Set Details
Format:
LDR rt, offset(base)
Description:
This instruction can be used in combination with the LDL instruction to
load a register with eight consecutive bytes from memory, when the bytes
cross a doubleword boundary. LDR loads the right portion of the register
with the appropriate part of the low-order doubleword; LDL loads the left
portion of the register with the appropriate part of the high-order
doubleword.
The LDR instruction adds its sign-extended 16-bit offset to the contents of
general register base to form a virtual address which can specify an
arbitrary byte. It reads bytes only from the doubleword in memory which
contains the specified starting byte. From one to eight bytes will be
loaded, depending on the starting byte specified.
Conceptually, it starts at the specified byte in memory and loads that byte
into the low-order (right-most) byte of the register; then it loads bytes from
memory into the register until it reaches the high-order byte of the
doubleword in memory. The most significant (left-most) byte(s) of the
register will not be changed.
LDR
Load Doubleword Right
31 2526 2021 1516 0
LDR
base rt
offset
655 16
0 1 1 0 1 1
LDR
A
LDR $24,4($0)
after
address 0
address 8
register
$24
(big-endian)
before
10234567
98 101112131415
BCDEFGH
A
register
$24
BC0 1 2 34
memory