Mips Technologies R4000 - Page 561

MIPS R4000 Microprocessor User's Manual A-93
CPU Instruction Set Details
Format:
LHU rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. The contents of the halfword at the
memory location specified by the effective address are zero-extended and
loaded into general register rt.
If the least-significant bit of the effective address is non-zero, an address
error exception occurs.
Operation:
Exceptions:
TLB refill exception TLB invalid exception
Bus Error exception Address error exception
LHU
Load Halfword Unsigned
31 2526 2021 1516 0
LHU base rt
offset
655 16
1 0 0 1 0 1
LHU
32 T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
mem ← LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte ← vAddr
2...0
xor (BigEndianCPU
2
|| 0)
GPR[rt] ← 0
16
|| mem
15+8*byte...8*byte
pAddr ← pAddr
PSIZE – 1...3
|| (pAddr
2...0
xor (ReverseEndian
2
|| 0))
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
mem ← LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte ← vAddr
2...0
xor (BigEndianCPU
2
|| 0)
GPR[rt] ← 0
48
|| mem
15+8*byte...8*byte
pAddr ← pAddr
PSIZE – 1...3
|| (pAddr
2...0
xor (ReverseEndian
2
|| 0))