Appendix A
A-94 MIPS R4000 Microprocessor User's Manual
Format:
LL rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. The contents of the word at the
memory location specified by the effective address are loaded into general
register rt. In 64-bit mode, the loaded word is sign-extended.
The processor begins checking the accessed word for modification by
other processor and devices.
Load Linked and Store Conditional can be used to atomically update
memory locations as shown:
This atomically increments the word addressed by T0. Changing the ADD
to an OR changes this to an atomic bit set. This instruction is available in
User mode, and it is not necessary for CP0 to be enabled.
The operation of LL is undefined if the addressed location is uncached
and, for synchronization between multiple processors, the operation of LL
is undefined if the addressed location is noncoherent. A cache miss that
occurs between LL and SC may cause SC to fail, so no load or store
operation should occur between LL and SC, otherwise the SC may never
be successful. Exceptions also cause SC to fail, so persistent exceptions
must be avoided. If either of the two least-significant bits of the effective
address are non-zero, an address error exception takes place.
LL
Load Linked
31 2526 2021 1516 0
LL base rt
offset
655 16
1 1 0 0 0 0
LL
L1:
LL T1, (T0)
ADD T2, T1, 1
SC T2, (T0)
BEQ T2, 0, L1
NOP
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