Mips Technologies R4000 - Page 563

MIPS R4000 Microprocessor User's Manual A-95
CPU Instruction Set Details
Operation:
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
(continued)
LL
Load Linked
LL
32 T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
mem ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
GPR[rt] ← mem
31+8*byte...8*byte
LLbit ← 1
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
mem ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
GPR[rt] ← (mem
31+8*byte
)
32
|| mem
31+8*byte...8*byte
LLbit ← 1
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
))
byte ← vAddr
2...0
xor (BigEndianCPU || 0
2
)
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
))
byte ← vAddr
2...0
xor (BigEndianCPU || 0
2
)