Appendix A
A-96 MIPS R4000 Microprocessor User's Manual
Format:
LLD rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. The contents of the doubleword at
the memory location specified by the effective address are loaded into
general register rt.
The processor begins checking the accessed word for modification by
other processor and devices.
Load Linked Doubleword and Store Conditional Doubleword can be used
to atomically update memory locations:
This atomically increments the word addressed by T0. Changing the ADD
to an OR changes this to an atomic bit set.
LLD
Load Linked Doubleword
31 2526 2021 1516 0
LLD base rt
offset
655 16
1 1 0 1 0 0
LLD
L1:
LLD T1, (T0)
ADD T2, T1, 1
SCD T2, (T0)
BEQ T2, 0, L1
NOP
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