MIPS R4000 Microprocessor User's Manual A-97
CPU Instruction Set Details
The operation of LLD is undefined if the addressed location is uncached
and, for synchronization between multiple processors, the operation of
LLD is undefined if the addressed location is noncoherent. A cache miss
that occurs between LLD and SCD may cause SCD to fail, so no load or
store operation should occur between LLD and SCD, otherwise the SCD
may never be successful. Exceptions also cause SCD to fail, so persistent
exceptions must be avoided.
This instruction is available in User mode, and it is not necessary for CP0
to be enabled.
If any of the three least-significant bits of the effective address are non-
zero, an address error exception takes place.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
Reserved instruction exception (R4000 in 32-bit mode)
(continued)
LLD
Load Linked Doubleword
LLD
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
mem ← LoadMemory (uncached, DOUBLEWORD, pAddr, vAddr, DATA)
GPR[rt] ← mem
LLbit ← 1
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