MIPS R4000 Microprocessor User's Manual A-99
CPU Instruction Set Details
Format:
LW rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. The contents of the word at the
memory location specified by the effective address are loaded into general
register rt. In 64-bit mode, the loaded word is sign-extended. If either of
the two least-significant bits of the effective address is non-zero, an
address error exception occurs.
Operation:
Exceptions:
TLB refill exception TLB invalid exception
Bus error exception Address error exception
LW
Load Word
31 2526 2021 1516 0
LW base rt
offset
655 16
1 0 0 0 1 1
LW
32 T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
mem ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
GPR[rt] ← mem
31+8*byte...8*byte
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
mem ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
GPR[rt] ← (mem
31+8*byte
)
32
|| mem
31+8*byte...8*byte
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
))
byte ← vAddr
2...0
xor (BigEndianCPU || 0
2
)
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
))
byte ← vAddr
2...0
xor (BigEndianCPU || 0
2
)
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