Mips Technologies R4000 - Page 571

MIPS R4000 Microprocessor User's Manual A-103
CPU Instruction Set Details
The contents of general register rt are internally bypassed within the
processor so that no NOP is needed between an immediately preceding
load instruction which specifies register rt and a following LWL (or LWR)
instruction which also specifies register rt. No address exceptions due to
alignment are possible.
Operation:
(continued)
LWL
Load Word Left
LWL
pAddr ← pAddr
PSIZE–1...2
|| 0
2
32 T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
endif
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE–1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
GPR[rt] ← (temp
31
)
32
|| temp
mem ← LoadMemory (uncached, 0 || byte, pAddr, vAddr, DATA)
temp ← mem
32*word+8*byte+7...32*word
|| GPR[rt]
23-8*byte...0
if BigEndianMem = 0 then
byte ← vAddr
1...0
xor BigEndianCPU
2
word ← vAddr
2
xor BigEndianCPU
if BigEndianMem = 0 then
pAddr ← pAddr
PSIZE–1...2
|| 0
2
endif
byte ← vAddr
1...0
xor BigEndianCPU
2
word ← vAddr
2
xor BigEndianCPU
pAddr ← pAddr
PSIZE–1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
mem ← LoadMemory (uncached, 0 || byte, pAddr, vAddr, DATA)
temp ← mem
32*word+8*byte+7...32*word
|| GPR[rt]
23-8*byte...0
GPR[rt] ← temp