Mips Technologies R4000 - Page 593

MIPS R4000 Microprocessor User's Manual A-125
CPU Instruction Set Details
Format:
SB rt, offset(base)
Description:
The 16-bit offset is sign-extended and added to the contents of general
register base to form a virtual address. The least-significant byte of register
rt is stored at the effective address.
Operation:
Exceptions:
TLB refill exception
TLB invalid exception
TLB modification exception
Bus error exception
Address error exception
SB
Store Byte
31 2526 2021 1516 0
SB base rt
offset
655 16
1 0 1 0 0 0
SB
32 T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
StoreMemory (uncached, BYTE, data, pAddr, vAddr, DATA)
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
byte ← vAddr
2...0
xor BigEndianCPU
3
data ← GPR[rt]
63–8*byte...0
|| 0
8*byte
StoreMemory (uncached, BYTE, data, pAddr, vAddr, DATA)
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
byte ← vAddr
2...0
xor BigEndianCPU
3
data ← GPR[rt]
63–8*byte...0
|| 0
8*byte
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor ReverseEndian
3
)