Mips Technologies R4000 - Page 602

Appendix A
A-134 MIPS R4000 Microprocessor User's Manual
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
SDL
S
tore
D
ou
bl
ewor
d
L
e
f
t
SDL
(continued)
endif
If BigEndianMem = 0 then
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
data ← 0
56–8*byte
|| GPR[rt]
63...56–8*byte
pAddr ← pAddr
31...3
|| 0
3
Storememory (uncached, byte, data, pAddr, vAddr, DATA)
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE –1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
byte ← vAddr
2...0
xor BigEndianCPU
3