Appendix A
A-136 MIPS R4000 Microprocessor User's Manual
Format:
SDR rt, offset(base)
Description:
This instruction can be used with the SDL instruction to store the contents
of a register into eight consecutive bytes of memory, when the bytes cross
a boundary between two doublewords. SDR stores the right portion of the
register into the appropriate part of the low-order doubleword; SDL stores
the left portion of the register into the appropriate part of the low-order
doubleword of memory.
The SDR instruction adds its sign-extended 16-bit offset to the contents of
general register base to form a virtual address which may specify an
arbitrary byte. It alters only the word in memory which contains that byte.
From one to eight bytes will be stored, depending on the starting byte
specified.
Conceptually, it starts at the least-significant (rightmost) byte of the
register and copies it to the specified byte in memory; then it copies bytes
from register to memory until it reaches the high-order byte of the word in
memory. No address exceptions due to alignment are possible.
31 2526 2021 1516 0
SDR base rt
offset
655 16
1 0 1 1 0 1
SDR
Store Doubleword Right
SDR
SDR $24,4($0)
after
A
address 0
address 8
register
$24
(big-endian)
before
BCDEFGH
memory
address 0
address 8
(big-endian)
memory
10234567
98101112131415
4567
98 101112131415
EF GH
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