MIPS R4000 Microprocessor User's Manual A-137
CPU Instruction Set Details
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
SDR
tore
ou
ewor
g
t
SDR
(continued)
endif
If BigEndianMem = 0 then
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
data ← GPR[rt]
63–8*byte
|| 0
8*byte
pAddr ← pAddr
PSIZE – 31...3
|| 0
3
StoreMemory (uncached, DOUBLEWORD-byte, data, pAddr, vAddr, DATA)
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE – 1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
byte ← vAddr
1...0
xor BigEndianCPU
3
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