Mips Technologies R4000 - Page 624

Appendix A
A-156 MIPS R4000 Microprocessor User's Manual
Operation:
SWL
Store Word Left
SWL
(Continued)
32 T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE – 1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
If BigEndianMem = 0 then
pAddr ← pAddr
31...2
|| 0
2
endif
byte ← vAddr
1...0
xor BigEndianCPU
2
if (vAddr
2
xor BigEndianCPU) = 0 then
data ← 0
32
|| 0
24-8*byte
|| GPR[rt]
31...24-8*byte
else
data ← 0
24-8*byte
|| GPR[rt]
31...24-8*byte
|| 0
32
endif
Storememory (uncached, byte, data, pAddr, vAddr, DATA)
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE – 1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
If BigEndianMem = 0 then
pAddr ← pAddr
31...2
|| 0
2
endif
byte ← vAddr
1...0
xor BigEndianCPU
2
if (vAddr
2
xor BigEndianCPU) = 0 then
data ← 0
32
|| 0
24-8*byte
|| GPR[rt]
31...24-8*byte
else
data ← 0
24-8*byte
|| GPR[rt]
31...24-8*byte
|| 0
32
endif
StoreMemory(uncached, byte, data, pAddr, vAddr, DATA)