Mips Technologies R4000 - Page 637

MIPS R4000 Microprocessor User's Manual A-169
CPU Instruction Set Details
Format:
TLBP
Description:
The Index register is loaded with the address of the TLB entry whose
contents match the contents of the EntryHi register. If no TLB entry
matches, the high-order bit of the Index register is set.
The architecture does not specify the operation of memory references
associated with the instruction immediately after a TLBP instruction, nor
is the operation specified if more than one TLB entry matches.
Operation:
Exceptions:
Coprocessor unusable exception
TLBP
Probe TLB For Matching Entry
0
6
6 531 25 2426
COP0
6
0
TLBP
191
CO
0 1 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01
TLBP
32 T: Index← 1 || 0
25
|| undefined
6
for i in 0...TLBEntries–1
if (TLB[i]
95...77
= EntryHi
31...12)
and (TLB[i]
76
or
(TLB[i]
71...64
= EntryHi
7...0
)) then
Index ← 0
26
|| i
5...0
endif
endfor
64 T: Index← 1 || 0
25
|| undefined
6
for i in 0...TLBEntries–1
if (TLB[i]
167...141
and not (0
15
|| TLB[i]
216...205
))
= EntryHi
39...13
) and not (0
15
|| TLB[i]
216...205
)) and
(TLB[i]
140
or (TLB[i]
135...128
= EntryHi
7...0
)) then
Index ← 0
26
|| i
5...0
endif
endfor