Mips Technologies R4000 - Page 638

Appendix A
A-170 MIPS R4000 Microprocessor User's Manual
Format:
TLBR
Description:
The G bit (which controls ASID matching) read from the TLB is written
into both of the EntryLo0 and EntryLo1 registers.
The EntryHi and EntryLo registers are loaded with the contents of the TLB
entry pointed at by the contents of the TLB Index register. The operation
is invalid (and the results are unspecified) if the contents of the TLB Index
register are greater than the number of TLB entries in the processor.
Operation:
Exceptions:
Coprocessor unusable exception
TLBR
Read Indexed TLB Entry
0
6
6 531 25 2426
COP0
6
0
TLBR
191
CO
0 1 0 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01
TLBR
32 T: PageMask ← TLB[Index
5...0
]
127...96
EntryHi ← TLB[Index
5...0
]
95...64
and not TLB[Index
5...0
]
127...96
EntryLo1 ←TLB[Index
5...0
]
63...32
EntryLo0 ← TLB[Index
5...0
]
31...0
64 T: PageMask ← TLB[Index
5...0
]
255...192
EntryHi ← TLB[Index
5...0
]
191...128
and not TLB[Index
5...0
]
255...192
EntryLo1 ←TLB[Index
5...0
]
127...65
|| TLB[Index
5...0
]
140
EntryLo0 ← TLB[Index
5...0
]
63...1
|| TLB[Index
5...0
]
140