Mips Technologies R4000 - Page 650

Appendix A
A-182 MIPS R4000 Microprocessor User's Manual
Figure A-2 (cont.) R4000 Opcode Bit Encoding
Key:
* Operation codes marked with an asterisk cause reserved
instruction exceptions in all current implementations and are
reserved for future versions of the architecture.
γ Operation codes marked with a gamma cause a reserved
instruction exception. They are reserved for future versions of the
architecture.
δ Operation codes marked with a delta are valid only for R4000
processors with CP0 enabled, and cause a reserved instruction
exception on other processors.
φ Operation codes marked with a phi are invalid but do not cause
reserved instruction exceptions in R4000 implementations.
ξ Operation codes marked with a xi cause a reserved instruction
exception on R4000 processors.
χ Operation codes marked with a chi are valid only on R4000.
ε Operation codes marked with epsilon are valid when the processor
is operating either in the Kernel mode or in the 64-bit non-Kernel
(User or Supervisor) mode. These instructions cause a reserved
instruction exception if 64-bit operation is not enabled in User or
Supervisor mode.
BCF
18...16
01234567
20...19
0
1
2
3
BCFL
γγ γ γ γγ γ
γγ
BCT
BCTL
γγ
γ
γγ γ γ γγ γγ
γγ γ γ γγ γγ
CP0 Function
2 ... 0
01234567
5 ... 3
0
1
2
3
TLBWI
TLBR
TLBWR
TLBP
ξ
0
1
2
3
ERET
χ
φφφ
φφ φ φ φφ φφ
φφ
φφ φ φ φφ φφ
φφ φ φ φφ φφ
φφ φ φ φφ φφ
φφ φ φ φφ φ
φφ φ φ φφ φ
φφ φ φ φφ φ
COPz rt