Appendix B
B-14 MIPS R4000 Microprocessor User's Manual
Format:
ADD.fmt fd, fs, ft
Description:
The contents of the FPU registers specified by fs and ft are interpreted in
the specified format and arithmetically added. The result is rounded as if
calculated to infinite precision and then rounded to the specified format
(fmt), according to the current rounding mode. The result is placed in the
floating-point register (FPR) specified by fd.
This instruction is valid only for single- and double-precision floating-
point formats. The operation is not defined if bit 0 of any register
specification is set and the FR bit in the Status register equals zero, since
the register numbers specify an even-odd pair of adjacent coprocessor
general registers. When the FR bit in the Status register equals one, both
even and odd register numbers are valid.
Operation:
Exceptions:
Coprocessor unusable exception
Floating-Point exception
Coprocessor Exceptions:
Unimplemented operation exception
Invalid operation exception
Inexact exception
Overflow exception
Underflow exception
ADD.fmt
Floating-Point Add
31 0
655556
COP1 fmt ft fs fd ADD
11 1021 20 16 1526 25 6 5
0 1 0 0 0 1 0 0 0 0 0 0
ADD.fmt
T: StoreFPR (fd, fmt, ValueFPR(fs, fmt) + ValueFPR(ft, fmt))
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