Mips Technologies R4000 - Page 741

MIPS R4000 Microprocessor User's Manual I-1
Index
Numerics
32-bit
addressing 109
applications 9
data format 24
instructions 36
operands, in 64-bit mode 39
operations 6, 67
single-precision FP format 164
virtual-to-physical-address
translation 65
32-bit mode
address space 31
address translation 65, 95
addresses 63
FPU operations 153
TLB entry format 81
4th Floor
B-dorm. See Alco Hall
64-bit
addressing 109
ALU 9
bus, address and data 201
data format 24
double-precision FP format 164
floating-point registers 156
FPU 9
internal data path widths 381
operations 6, 39, 67
System interface 11
virtual-to-physical-address
translation 66
64-bit mode
32-bit operands, handling of 39
address space 31
address translation 66, 95
addresses 63
FPU operations 153
TLB entry format 81
A
address acceleration 58
Address Error exception 127
address prediction 58
address space identifier (ASID) 64
address spaces
32-bit translation of 65
64-bit translation of 66
address space identifier (ASID) 64
physical 64
virtual 63
virtual-to-physical translation of 64
addressing
and data formats 24
big-endian 24
Kernel mode 73
little-endian 24
misaligned data 26
Supervisor mode 69
User mode 67
virtual address translation 95
See also address spaces
Alco Hall vs. Acid. See game, softball
application software, compatibility with
MIPS R2000, R3000, and R6000
processors 6
architecture
64-bit 9
superpipeline 11
array, page table entry (PTE) 102
ASID. See address space identifier