Mips Technologies R4000 - Page 742

Index
I-2 MIPS R4000 Microprocessor User's Manual
B
Bad Virtual Address register (BadVAddr)
103
big-endian, byte addressing 24, 170
binary fixed-point format 166
bit definition of
ERL 68, 69, 73, 109
EXL 68, 69, 73, 109, 112, 119
IE 109
KSU 68, 69, 73
KX 73, 109
SX 69, 109
UX 68, 109
boot-mode settings 222
boundary scanning 390
Boundary-scan register 394
branch delay 48
branch instructions, CPU 15, 41
branch instructions, FPU 170
Breakpoint exception 138
Bus Error exception 134
Bypass register 393
byte addressing
big-endian 24, 170
little-endian 24, 170
byte ordering 24
big-endian 24
in doublewords 25
little-endian 24
C
cache 33
Cache Error (CacheErr) register 116
Cache Error exception 132
Cache Error exception process 120
caches
attributes
clean 255
clean exclusive 256
dirty 255
dirty exclusive 256
dirty shared 255
exclusive 255
invalid 255
shared 255
coherency
attributes 264
conflicts 271–285
maintaining coherency on load
and store operations 269
protocol, overview 264
synchronization 286
description 246
line ownership 258
manipulation by an external agent 270
mapping states between caches 257
memory hierarchy 32, 244
misses
address prediction 58
handling 49
performance considerations 58
pipeline back-up 54
on-chip instruction and data caches 33
on-chip primary caches 33, 246
operation modes 266
optional external secondary cache 32
ordering constraints 267
overview of operations 245
primary cache, states 256
primary data cache
accessing 251
line size 250
primary instruction cache
accessing 251
line size 249
secondary cache
accessing 254
line size 252
organization 252
states 256