NXP Semiconductors KL25 Series - Page 20

Section number Title Page
28.5 Initialization information..............................................................................................................................................499
28.5.1 ADC module initialization example............................................................................................................499
28.6 Application information................................................................................................................................................501
28.6.1 External pins and routing.............................................................................................................................501
28.6.2 Sources of error............................................................................................................................................503
Chapter 29
Comparator (CMP)
29.1 Introduction...................................................................................................................................................................509
29.2 CMP features................................................................................................................................................................509
29.3 6-bit DAC key features.................................................................................................................................................510
29.4 ANMUX key features...................................................................................................................................................511
29.5 CMP, DAC and ANMUX diagram...............................................................................................................................511
29.6 CMP block diagram......................................................................................................................................................512
29.7 Memory map/register definitions..................................................................................................................................514
29.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................514
29.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................515
29.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................517
29.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................517
29.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................518
29.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................519
29.8 Functional description...................................................................................................................................................520
29.8.1 CMP functional modes.................................................................................................................................520
29.8.2 Power modes................................................................................................................................................529
29.8.3 Startup and operation...................................................................................................................................530
29.8.4 Low-pass filter.............................................................................................................................................531
29.9 CMP interrupts..............................................................................................................................................................533
29.10 DMA support................................................................................................................................................................533
29.11 CMP Asyncrhonous DMA support...............................................................................................................................534
29.12 Digital-to-analog converter...........................................................................................................................................534
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
20 Freescale Semiconductor, Inc.