NXP Semiconductors KL25 Series - Page 29

Section number Title Page
38.4.4 System management bus specification........................................................................................................709
38.4.5 Resets...........................................................................................................................................................712
38.4.6 Interrupts......................................................................................................................................................712
38.4.7 Programmable input glitch filter..................................................................................................................714
38.4.8 Address matching wakeup...........................................................................................................................715
38.4.9 DMA support...............................................................................................................................................715
38.5 Initialization/application information...........................................................................................................................716
Chapter 39
Universal Asynchronous Receiver/Transmitter (UART0)
39.1 Introduction...................................................................................................................................................................721
39.1.1 Features........................................................................................................................................................721
39.1.2 Modes of operation......................................................................................................................................722
39.1.3 Block diagram..............................................................................................................................................722
39.2 Register definition.........................................................................................................................................................724
39.2.1 UART Baud Rate Register High (UARTx_BDH).......................................................................................725
39.2.2 UART Baud Rate Register Low (UARTx_BDL)........................................................................................726
39.2.3 UART Control Register 1 (UARTx_C1).....................................................................................................726
39.2.4 UART Control Register 2 (UARTx_C2).....................................................................................................728
39.2.5 UART Status Register 1 (UARTx_S1)........................................................................................................729
39.2.6 UART Status Register 2 (UARTx_S2)........................................................................................................731
39.2.7 UART Control Register 3 (UARTx_C3).....................................................................................................733
39.2.8 UART Data Register (UARTx_D)...............................................................................................................734
39.2.9 UART Match Address Registers 1 (UARTx_MA1)....................................................................................735
39.2.10 UART Match Address Registers 2 (UARTx_MA2)....................................................................................736
39.2.11 UART Control Register 4 (UARTx_C4).....................................................................................................736
39.2.12 UART Control Register 5 (UARTx_C5).....................................................................................................737
39.3 Functional description...................................................................................................................................................738
39.3.1 Baud rate generation....................................................................................................................................738
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 29