Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009
05/09/08 4.2 Revised clock routing resources in “BUFGCTRL to DCM,” page 73.
Removed example Figure 2-10 on page 76.
Corrected note 1 in Table 4-5, page 124.
Added “Legal Block RAM and FIFO Combinations,” page 171.
Clarified Note 7 in DCI in Virtex-5 Device I/O Standards. Master DCI is not supported
in Banks 1 and 2.
09/23/08 4.3 Added the TXT platform to Table 1-5, Table 2-1, and Table 5-2.
Chapter 2: Revised “Reset Input - RST” on page 53 and “System-Synchronous Setting
(Default),” page 66.
Chapter 3: Updated “Jitter Filter,” page 94.
Chapter 4: Updated “Write Modes” on page 117 and “Asynchronous Clocking” on
page 119.
Chapter 6: Labeled all the DCI_18 standards consistently in Table 6-39 and Table 6-40.
Replaced the link to the “Full Device SSO Calculator.”
Chapter 8: Updated CLKB in Table 8-1, page 355 and “High-Speed Clock Input - CLKB,”
page 357.
12/02/08 4.4 Chapter 2: Changed “edge” to “half” in IBUFG – Global Clock Input Buffer description
on page 51, page 52, and page 53.
Chapter 4: Added new text and equation to “Almost Empty Flag,” page 146. Added note
1 to Table 4-19, page 148.
Chapter 5: Changed RAM#XM to RAM#M in Figure 5-32, page 212.
Chapter 6: Corrected PCI acronym definition in “PCI-X, PCI-33, PCI-66 (Peripheral
Component Interconnect),” page 247. Added to the description of the SSTL18_II_T_DCI
standard in “SSTL18_II_T_DCI (1.8V) Split-Thevenin Termination,” page 293.
Chapter 7: Added mode to caption of Figure 7-7, page 323 for clarification.
Chapter 8: Added statement about shared resources between OCLK and CLK in “High-
Speed Clock for Strobe-Based Memory Interfaces - OCLK,” page 357.
01/09/09 4.5 Chapter 4: Revised the paragraph below Equation 4-1 on page 146.
Chapter 6: Added IBUFDS_DIFF_OUT to the list of primitive names for differential I/O
standards in “Virtex-5 FPGA SelectIO Primitives,” page 233. Added new section
“IBUFDS_DIFF_OUT,” page 235.
Chapter 7: In the Verilog code segment for bidirectional IODELAY on page 333, corrected
the setting of RST.
03/19/09 4.6 Chapter 3: Added reference to the Virtex-5 FPGA Configuration Guide in “PLL_ADV
Primitive,” page 93.
Chapter 4: In the second paragraph of “Write Modes,” page 117, added “in ECC
configuration” after READ_FIRST.
Chapter 5: In the third sentence of the second paragraph of “Look-Up Table (LUT),” page
178, changed “slices” to “LUTs”. Removed MC31 and SHIFTOUT from the bottom
SRL32 in Figure 5-19, page 193.
Chapter 6: Inserted sentence about at least one I/O being configured as DCI to the
paragraph after Figure 6-4, page 220.
Date Version Revision

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English