Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Page xv
Receive BD Standard Producer Ring Index Register (Offset 0x268–0x26F)...................................... 239
Receive BD Return Ring 1 Consumer Index Register (Offset 0x284–0x287)..................................... 239
Receive BD Return Ring 2 Consumer Index Register (Offset 0x28C–0x28F).................................... 239
Receive BD Return Ring 3 Consumer Index Register (Offset 0x294–0x297)..................................... 239
Receive BD Return Ring 4 Consumer Index Register (Offset 0x29C–0x29F).................................... 240
Send BD Ring Host Producer Index Register (Offset 0x300–0x307).................................................. 240
Ethernet MAC Control Registers ............................................................................................................ 241
Ethernet MAC Mode Register (Offset 0x400) ..................................................................................... 245
Ethernet MAC Status Register (Offset 0x404) .................................................................................... 246
Ethernet MAC Event Enable Register (Offset 0x408)......................................................................... 247
LED Control Register (Offset 0x40C).................................................................................................. 247
Ethernet MAC Addresses Registers (Offset 0x410–0x42C)............................................................... 249
WOL Pattern Pointer Register (Offset 0x430).....................................................................................249
WOL Pattern Configuration Register (Offset 0x434)........................................................................... 250
Ethernet Transmit Random Backoff Register (Offset 0x438).............................................................. 250
Receive MTU Size Register (Offset 0x43C)........................................................................................250
MI Communication Register (Offset 0x44C) ....................................................................................... 251
MI Status Register (Offset 0x450)....................................................................................................... 251
MI Mode Register (Offset 0x454)........................................................................................................ 252
Autopolling Status Register (Offset 0x458)......................................................................................... 252
Transmit MAC Mode Register (Offset 0x45C) .................................................................................... 253
Transmit MAC Status Register (Offset 0x460).................................................................................... 253
Transmit MAC Lengths Register (Offset 0x464)................................................................................. 254
Receive MAC Mode Register (Offset 0x468)...................................................................................... 254
Receive MAC Status Register (Offset 0x46C) .................................................................................... 256
MAC Hash Register 0–3 (Offset 0x470–0x47C)................................................................................. 256
Receive Rules Control Registers (Offset Rule N: 0x480 + 8*N) ......................................................... 257
Receive Rules Value/Mask Registers (Offset Rule N: 0x484 + 8*N).................................................. 258
Receive Rules Configuration Register (Offset 0x500) ........................................................................ 258
Low Watermark Maximum Receive Frames Register (Offset 0x504)................................................. 258
Ethernet Type Matching Value Register (Offset 0x510)...................................................................... 259
Protocol ID Offset Register (Offset 0x514) ......................................................................................... 259
Regulator Voltage Control Register (Offset 0x590)............................................................................. 260
Indirection Table Register 0 (Offset: 0x630) ....................................................................................... 261
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