Broadcom BCM5722 - Page 14

BCM5722 Programmer’s Guide
10/15/07
PCIe-Enhanced Capabilities ....................................................................................................................224
Advanced Error Reporting Enhanced Capability Header Register (Offset 0x100)..............................224
Uncorrectable Error Status Register (Offset 0x104)............................................................................224
Uncorrectable Error Mask Register (Offset 0x108) .............................................................................225
Uncorrectable Error Severity Register (Offset 0x10C) ........................................................................226
Correctable Error Status Register (Offset 0x110)................................................................................227
Correctable Error Mask Register (Offset 0x114).................................................................................227
Advanced Error Capabilities and Control Register (Offset 0x118) ......................................................227
Header Log Register (Offset 0x11C–0x12B).......................................................................................228
Virtual Channel Enhanced Capability Header (Offset 0x13c)..............................................................228
Port VC Capability Register (Offset 0x140).........................................................................................228
Port VC Capability Register 2 (Offset 0x144)......................................................................................228
Port VC Control Register (Offset 0x148) .............................................................................................228
Port VC Status Register (Offset 0x14A) ..............................................................................................229
VC Resource Capability Register (Offset 0x14C)................................................................................229
VC Resource Control Register (Offset 0x150) ....................................................................................229
VC Resource Status Register (Offset 0x154)......................................................................................229
Device Serial No Enhanced Capability Header Register (Offset 0x160).............................................230
Device Serial No Lower DW Register (Offset 0x164)..........................................................................230
Device Serial No Upper DW Register (Offset 0x168)..........................................................................231
Power Budgeting Enhanced Capability Header Register (Offset 0x16C)............................................231
Power Budgeting Data Select Register (Offset 0x170) .......................................................................231
Power Budgeting Data Register (Offset 0x174) ..................................................................................232
Power Budgeting Capability Register (Offset 0x178) ..........................................................................232
Firmware Power Budgeting Register 1 (Offset 0x17C) .......................................................................233
Firmware Power Budgeting Register 2 (Offset 0x17E)........................................................................233
Firmware Power Budgeting Register 3 (Offset 0x180)........................................................................234
Firmware Power Budgeting Register 4 (Offset 0x182)........................................................................234
Firmware Power Budgeting Register 5 (Offset 0x184)........................................................................235
Firmware Power Budgeting Register 6 (Offset 0x186)........................................................................235
Firmware Power Budgeting Register 7 (Offset 0x188)........................................................................236
Firmware Power Budgeting Register 8 (Offset 0x18A)........................................................................236
PCIe 1.1 Advisory Non-Fatal Error Masking (Offset: 0x18C) ..............................................................237
High-Priority Mailboxes............................................................................................................................238
Interrupt Mailbox 0 Register (Offset 0x200–0x207).............................................................................238