Broadcom BCM5722 - Page 13

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Page xiii
Device Serial No Upper DW Override Register (Offset: 0x64)............................................................ 203
Miscellaneous Host Control Register (Offset 0x68) ............................................................................ 204
DMA Read/Write Control Register (Offset 0x6C)................................................................................ 205
PCI State Register (Offset 0x70) ........................................................................................................ 206
PCI Clock Control Register (Offset 0x74) ........................................................................................... 207
Register Base Address Register (Offset 0x78)................................................................................... 209
Memory Window Base Address Register (Offset 0x7C) ..................................................................... 210
Register Data Register (Offset 0x80).................................................................................................. 211
Memory Window Data Register (Offset 0x84)..................................................................................... 211
Expansion ROM Registers ...................................................................................................................... 212
Expansion ROM BAR Size Register (Offset 0x88) ............................................................................. 212
Expansion ROM Address Register (Offset 0x8C)............................................................................... 212
Expansion ROM Data Register (Offset 0x90) ..................................................................................... 213
VPD Config Register ................................................................................................................................213
VPD Interface Register (Offset 0x94) ................................................................................................. 213
UNDI Mailbox Registers........................................................................................................................... 214
UNDI Receive BD Standard Producer Ring Producer Index Mailbox (Offset 0x98) ........................... 214
UNDI Receive Return Ring Consumer Index Mailbox (Offset 0xA0).................................................. 214
UNDI Send BD Producer Index Mailbox (Offset 0xA8)....................................................................... 214
PCIe Capabilities...................................................................................................................................... 215
PCIe Capability List Register (Offset 0xD0)........................................................................................ 215
PCIe Next Capabilities Pointer Register (Offset 0xD1)....................................................................... 215
PCIe Capabilities Register (Offset 0xD2)............................................................................................ 215
Device Capabilities Register (Offset 0xD4)......................................................................................... 216
Device Control Register (Offset 0xD8)................................................................................................ 217
Device Status Register (Offset 0xDA)................................................................................................. 218
Link Capabilities Register (Offset 0xDC)............................................................................................. 219
Link Control Register (Offset 0xE0) .................................................................................................... 220
Link Status Command Register (Offset 0xE2) .................................................................................... 220
Message Signaled Interrupts Capabilities............................................................................................. 221
MSI Capability ID Register (Offset 0xE8)............................................................................................ 221
MSI Next Capabilities Pointer Register (Offset 0xE9)......................................................................... 221
Message Control Register (Offset 0xEA)............................................................................................ 222
Message Address Register (Offset 0xEC) ..........................................................................................223
Message Data Register (Offset 0xF4) ................................................................................................ 223