Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Reset Page 92
RESET
A hardware reset initiated by the PCI reset signal will initialize all the PCI configuration registers and device MAC registers
to their default values. The driver reset via the Core Clock Blocks Reset bit (see “Miscellaneous Configuration Register
(Offset 0x6804)” on page 335) will also initialize all non-sticky registers to their default values. The content of the device
internal memory remains unchanged after warm reset (any reset with the power supplied to the device).
At the end of the reset, the on-chip RX RISC executes a small on chip ROM code. This code loads an executable image
contained in an attached NVRAM and referred to as the bootcode. This bootcode allows at least the following fields to be
initialized to different values to support product variations (for additional details, see Section 4: “NVRAM Configuration” on
page 41).
• Vendor ID
• Device ID
• Subsystem Vendor ID
• Subsystem Device ID
• Possible PHY initialization
The bootcode may have additional functionality such as PXE that must be acquiesced while the host software is running.
For instance, an NDIS driver issues a device reset via the Core Clock Blocks Reset bit (see Table 343 on page 335). After
the reset is completed, the RX RISC begins executing the bootcode as if the power was first applied to the device. However,
the NDIS driver must have a mechanism to prevent the PXE driver from running and the bootcode must be able to distinguish
between a power-on reset and a reset initiated by the host software. The host software and the bootcode could implement
a reset handshake by using shared memory at offset 0x0b50 as a software mailbox (see “Firmware Mailbox” on page 165).
FIRMWARE DOWNLOAD
FIRMWARE BINARY IMAGE
The RISC cores in the BCM5722 Ethernet controller chips execute the MIPS-2 instruction set. Broadcom uses a GNU tool
kit to create the firmware binary code. The output from the GNU build is a C language header file, which contains the machine
code for the embedded RISC cores. This manual does not cover the technology necessary to program the RISC cores.
However, programmers may need to download value-added firmware provided by Broadcom. One example of value added
firmware is TCP segmentation firmware that can be loaded from the host driver. This section provides the necessary
understanding of the header file, created by the Broadcom GNU tools. The programmer must understand the layout of the
header file, to accomplish a firmware download.
The following sections are located in the header file provided by Broadcom:
• t3FwText[]—Array of 32-bit words. This section contains the machine code (opcodes/operands) executed by the RISC
cores. This is the text section in the binary file, output by the GNU build process.
• t3FwRodata[]—Array of 32-bit words. This section contains the read-only data available to the code section of the
firmware.
• t3FwData[]—Array of 32-bit words. This section contains the local variables available to the code section of the
firmware.
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