BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 91 Shutdown Document 5722-PG101-R
SHUTDOWN
To power down the BCM5722 Ethernet controller, its state machines must be disabled in specific sequence as shown below.
The host software must clear the Enable bit of each state machine and poll the bit until it is cleared. The maximum poll period
that software must wait for the enable bits to clear is 2 ms; except, the read and write DMA mode registers require a
maximum timeout of 4 ms.
// Receive path shutdown sequence.
Receive_MAC_Mode.Enable = 0 // 0x0468
Receive_BD_Initiator_Mode.Enable = 0 // 0x2c00
Receive_List_Placement_Mode.Enable = 0 // 0x2000
Receive_Data_BD_Initiator_Mode.Enable = 0 // 0x2400
Receive_Data_Completion_Mode.Enable = 0 // 0x2800
Receive_BD_Completion_Mode.Enable = 0// 0x3000
// Transmit path shutdown sequence.
Send_BD_Selector_Mode.Enable = 0 // 0x1400
Send_BD_Initiator_Mode.Enable = 0 // 0x1800
Send_Data_Initiator_Mode.Enable = 0 // 0x0c00
Read_DMA_Mode.Enable = 0 // 0x4800
Send_Data_Completion_Mode.Enable = 0 // 0x1000
Send_BD_Completion_Mode.Enable = 0 // 0x1c00
MAC_Mode Register TDE bit (bit 21)= 0 // 0x0400
Transmit_MAC_Mode.Enable = 0// 0x045C
// Memory related state machines shutdown.
Host_Coalescing_Mode.Enable = 0 // 0x3c00
DMA_Write_Mode.Enable = 0 // 0x4c00
FTQ_Reset = 0xffffffff // 0x5c00
FTQ_Reset = 0 // 0x5c00
Note: The Buffer Manager and Memory Arbiter should not be disabled during shutdown. This is because the
scratch pad memory for the on-chip RISC processor of these MACs is reserved out of the RxMbuf memory
space.
To Next Page
Loading...