Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Page xxiii
NVM Arbitration Watchdog Timer Register (Offset 0x702C)............................................................... 376
NVM Auto-Sense Status Register (0x7038h) ..................................................................................... 377
BIST Registers.......................................................................................................................................... 378
BIST Control Register (Offset 0x7400) ............................................................................................... 378
BIST Status Register (Offset 0x7404)................................................................................................. 378
BIST Status Register (Offset 0x7404)................................................................................................. 379
PCIe Registers.......................................................................................................................................... 381
TLP Control Register (Offset 0x7C00) ................................................................................................ 383
Transaction Configuration Register (0x7C04).....................................................................................384
Write DMA Request Upper Address Diagnostic Register (Offset 0x7C10)......................................... 387
Write DMA Request Lower Address Diagnostic Register (Offset 0x7C14)......................................... 387
Write DMA Length/Byte Enable and Request Diagnostic Register (Offset 0x7C18) .......................... 388
Read DMA Request Upper Address Diagnostic Register (Offset 0x7C1C)........................................ 388
Read DMA Request Lower Address Diagnostic Register (Offset 0x7C20)......................................... 388
Read DMA Length and Request Diagnostic Register (Offset 0x7C24)............................................... 388
MSI DMA Request Upper Address Diagnostic Register (Offset 0x7C28)........................................... 389
MSI DMA Request Lower Address Diagnostic Register (Offset 0x7C2C) .......................................... 389
MSI DMA Length and Request Diagnostic Register (Offset 0x7C30)................................................. 389
Slave Request Length and Type Diagnostic Register (Offset 0x7C34).............................................. 390
Flow Control Inputs Diagnostic Register (Offset 0x7C38)................................................................... 390
XMT State Machines and Gated Requests Diagnostic Register (Offset 0x7C3C).............................. 391
Address ACK Xfer Count and ARB Length Diagnostic Register (Offset 0x7C40) .............................. 391
DMA Completion Header Diagnostic Register 0 (Offset 0x7C44)....................................................... 391
DMA Completion Header Diagnostic Register 1 (Offset 0x7C48)....................................................... 392
DMA Completion Header Diagnostic Register 2 (Offset 0x7C4C)...................................................... 392
DMA Completion Misc Diagnostic Register (Offset 0x7C50).............................................................. 392
DMA Completion Misc Diagnostic Register (Offset 0x7C54).............................................................. 393
DMA Completion Misc Diagnostic Register (Offset 0x7C58).............................................................. 393
Split Controller Requested Length and Address ACK Remaining Diagnostic Register (Offset 0x7C5C) .
393
Split Controller Misc 0 Register Diagnostic Register (Offset 0x7C60) ................................................ 394
Split Controller Misc 1 Register Diagnostic Register (Offset 0x7C64) ................................................ 394
TLP Bus, Dev, and Func Number Register (Offset 0x7C68) .............................................................. 394
TLP Debug Register (Offset 0x7C6C) ................................................................................................ 395
Data Link Control Register (Offset 0x7D00)........................................................................................ 395
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